High Q gyrator structures

ABSTRACT

The invention relates to a filter circuit and a method for making a filter circuit comprising at least one gyrator core section (GCi) having four inverters mutually connected in a loop configuration between a pair of input terminals (i —   1 ; i —   2 ) and a pair of output terminals (o —   1 ; o —   2 ). At least one common mode feedback section (CMIi, CMOi) is provided between the pair of input terminals and/or the pair of output terminals. The common mode feedback section comprises two series connections respectively formed by an inverter and a short-sectioned inverter connected antiparallelly between the input terminals or the output terminals. The inverters may be constituted by a MOS, CMOS or BiCMOS or bipolar transistor. According to the invention, the channel region dimensions of the transistors of the gyrator core section and/or the common mode feedback section are selected such that the relationship g*C≧g m *c m  is fulfilled, where g is the effective conductive loading of the gyrator core section terminals, C is the effective capacitive loading of the gyrator core section terminals, g m  is the effective gyration constant of the gyrator core section, and c m  is the effective transcapacitance of the gyrator core section.

FIELD OF THE INVENTION

The invention relates to a filter circuit consisting of at least onefilter stage in which amplifier-like circuits such as integrators and/orgyrators are employed to emulate the impedance of inductors. Theinvention also relates to a method for making (designing) such filtercircuit.

The invention in particular addresses the problem how complex (higherorder) filters can be designed such that the actual filtercharacteristics obtained in the practically realized filter circuitcoincide with the theoretically designed filter characteristics. Theinvention also addresses the problem how such complex (e.g. higherorder) filters can be designed such that they are stable.

BACKGROUND OF THE INVENTION

As shown in FIG. 1, typically a filter circuit consists of a pluralityof filter stages FST1 . . . FSTi wherein the first filter stage FST1 isdriven by a source, e.g. a current source CS and a source impedance SI,and the output of the last filter stage FSTi is terminated with anoutput impedance OI. As is well known to the skilled person the filtertransfer function is essentially a polynomial consisting of a pluralityof poles and zeros in the complex plane. Depending as to whether theindividual filter stages FSTi are a filter stage of first order orhigher order, a desired filter function and thus a desired filtercharacteristic can be obtained.

Hereinafter, it is assumed that each filter stage FSTi consists of asingle transistor or gyrator. However, of course the invention is notrestricted to each filter stage being of the said types but also higherorder filter stages may be used.

Depending on the desired filter transfer function, each filter stage isrealized by coils, resistors and capacitors. For example, on-chipfilters are normally restricted to resistor/capacitor filter stages,except at very high frequencies where on-chip coils of a few nH may beemployed. In such passive filter realizations (i.e. no active circuitryis employed in the filter stages FSTi) it therefore depends on howaccurate or whether at all coils (more particular the coil impedance)can be realized by a passive coil construction.

As is also well known to the skilled person in the art of filter design,active on-chip filters are often used to circumvent the coilrestrictions in passive filter circuits. In such active filtersamplifier-like circuitry is used to emulate the impedance of theinductors. That is, the coils are replaced by an active circuit. Forcontinuous-time filters such amplifier-like circuits typically consistof integrators or gyrators and for discrete-time circuits (digitalfilters) integrators are used for emulating the coils impedance.

Continuous-time filters implemented with integrators typically employsuch elements in loops and these loops. Two integrators in a loopactually form a gyrator. If the forward and backward integrators havethe same gain characteristics they form a passive gyrator and if they donot have the same gain characteristics they form an active (orasymmetric) gyrator. FIG. 2 shows a typical block diagram of a gyratorand its equivalent circuit diagram. The input voltage V1 and the outputvoltage V2 are linked via the gyration constant g_(m)* as I1=−g_(m)*V2and I2=g_(m)*V1. Thus, the gyrator shown in FIG. 2 consists of apositive transconductance g_(m)* and a negative transconductance−g_(m)*.

FIG. 3 shows a typical realization of the gyrator in FIG. 2 employing atleast one common mode feedback section CMIi, CMOi and a gyrator coresection GCi. As shown in FIG. 3, the negative transconductance −g_(m)*is typically formed by employing differential signals and crossing onepair of wires. That is, the gyrator core section GCi comprises fourinverters GI1 i-GI4 i mutually connected in a loop configuration betweena pair of input terminals i_1; i_2 and a pair of output terminals o_1;o_2. The common mode feedback section CMIi, CMOi is connected betweenthe pair of input terminals and/or the pair of output terminals andcomprises two series connections respectively formed by an inverterCMI1, CMO1 and a short-circuited inverter CMI2, CMO2 connectedantiparallely between said input terminals or said output terminals. Itshould be noted that one of the input or output common mode feedbacksections CMIi, CMOi is sufficient for realizing the positivetransconductance g_(m)* and that one gyrator core section GCi issufficient for realizing the negative transconductance −g_(m).

However, independent as to how the actual inverters are realized (byMOS, CMOS, BiCMOS or bipolar transistors), the crossing of the wiresresults in a loop through the four inverters GI1 i, GI2 i, GI3 i, GI4 i.FIG. 4 shows the realization of the inverters in FIG. 3 using two CMOStransistors T1 (e.g. NMOS) and T2 (e.g. PMOS) whose drains D and gates Gare connected with the respective sources connected to ground.Similarly, the short-sectioned inverters would correspond to the circuitconfiguration shown in FIG. 4 with the input In and the output Outconnected together.

Furthermore, gyrators realized by differential amplifier circuitry arepossible, as shown in FIGS. 5a, 5 b. FIG. 5a shows on the left-hand sidethe symbol for a transconductor realized by a differential amplifier andon right-hand side the inverter solution for such a differential typeamplifier in CMOS technology is shown. Two inverters I1, I2 (e.g. havinga circuit configuration as shown in FIG. 4) are respectively connectedto a first and second current source CS1, CS2 which are biased by biasvoltages bias1, bias2.

FIG. 5b shows the gyrator core section GCi of FIG. 3 using adifferential transconductor configuration as in FIG. 5a. As shown on theleft-hand side in FIG. 5b two differential transconductors DA1, DA2 areprovided in a feedback loop and therefore, using the circuitconfiguration in FIG. 5a, this leads to a structure similar to thatshown in FIG. 3, namely loop-like circuits in the gyrator core sectionGCi.

In FIG. 5b the circuit configuration of FIG. 5a is contained twiceleading to two first current sources CS1, CS12 and to second currentsources CS21, CS22, to first inverters I11, I12 and to second invertersI21, I22.

It should be noted that any gyrator configuration as shown in FIGS. 3,4, 5 may be used for the filter circuit according to the invention aswill be described below. That is, the present invention is notrestricted to any particular gyrator constructions. However, any gyratorconstruction would lead to the loop-like circuit of the gyrator coresection GCi as shown in FIG. 3. The only difference is that for thedifferential amplifier gyrator shown in FIG. 5b no common mode feedbackis needed because in the differential transconductor a high CMRR (CommonMode Rejection Ratio) exists.

As explained above, the loop-like configuration of the gyrator leads toa stability problem and the stability analysis of the gyrator- andintegrator-based filters is the same since the integrators are parts ofgyrator loops. An analysis of the gyrators is thus valid for theintegrator configuration as well.

DESCRIPTION OF THE PRIOR ART

The stability of filter circuits comprising a gyrator construction asshown in FIG. 3 has been studied by B. Nauta: “A CMOS transconductance-Cfilter technique for very high frequencies in IEEE Journal ofSolid-State Circuits, SC-27, pages 142-153, February 1992”. In thisprior art document the stability of the circuit in FIG. 3 (hereinaftercalled the Nauta cell) was conducted by assuming a MOS or CMOStransistor realization of the integrators in FIG. 3. As is well known tothe skilled person in the field of transistor technology, each MOS orCMOS transistor has a channel region of a particular dimension and thetime needed for transporting carriers through this channel (between thesource and drain) will influence the switching properties of the CMOS orMOS transistor.

In a PhD thesis which is the basis for the afore-mentioned IEEE paper,Nauta presented a number of simple filters and complexintermediate-frequency (IF) filters. The filter structures of lowerorder did work well but the more complex ones (higher order filters) hada very poor frequency response. In particular, the measured filtercharacteristics deviated from the theoretically expected filtercharacteristic to more than 10 dB. Furthermore, stability problemsoccurred and for making the filter circuits stable a separate Q-tuningcircuit (separate supply voltage for the ballast inverters in the commonmode feedback network) was used to enable an external adjustment.Basically, the adding of ballast devices or the sizing of the invertersin the common mode feedback sections reduces the dependence of thefilter circuit on the output conductance of the filter and thus leads tomore stable filter characteristics. Whilst Nauta achieved to make thefilter stable by the adding of the Q-tuning circuits, the filtercharacteristics significantly deviated from the expected behavior. Thus,obviously merely adding ballast inverters in the common mode feedbacknetwork is not sufficient to keep stability and achieve the desiredfilter characteristic. Furthermore, each individual gyrator wouldrequire a separate Q-tuning loop.

Lower-order filters comprising Nauta cells do work because the externalterminations provide a sufficient loading of the gyrator to make itstable. On the other hand, higher-order filters tend to have internalnodes that do not get sufficient loading to make the filter stable.

Thus, no complex active continuous-time on-chip MOS filter has beensuccessfully fabricated in products due to the unreliability of thegyrator cell in terms of stability and the only workable examples arelimited to lower-order filters or cascades of low-order filters (withinferior sensitivity characteristics).

SUMMARY OF THE INVENTION

Therefore, as explained above, the object of the present invention is toprovide a filter circuit comprising at least one filter stage includingat least one gyrator and a method for making such a filter circuit suchthat the filter circuit is stable also when higher-order filter stagesare used and such that the practically obtained filter characteristicmatches the theoretically expected filter characteristic.

This object is solved by the filter circuit (claim 11) consisting of atleast one filter stage which comprises: a gyrator core section havingfour inverters mutually connected in a loop configuration between a pairof input terminals and a pair of output terminals; at least one commonmode feedback section connected between the pair of input terminalsand/or the pair of output terminals and comprising two seriesconnections respectively formed by an inverter and a short-sectionedinverter connected antiparallely between said input terminals or saidoutput terminals; each of said inverters being constituted by at leastone MOS, CMOS or BiCMOS transistor having a gate, drain, source and achannel region between said drain and source; wherein the channel regiondimensions of the transistors of the gyrator core section and/or thecommon mode feedback section are selected such that the followingrelationship is fulfilled: g*C≧g_(m)*c_(m) where:

g: effective conductive loading of the gyrator core section terminals;C: effective capacitive loading of the gyrator core section terminals;g_(m): effective gyrating constant of the gyrator core section; andc_(m): effective transcapacitance of the gyrator core section.

Furthermore, this object is also solved by a method (claim 1) for makinga filter circuit consisting of at least one filter stage which comprisesthe following steps:

providing said at least one filter stage with a gyrator core sectionhaving four inverters mutually connected in a loop configuration betweena pair of input terminals and a pair of output terminals; and providingat least one common mode feedback section connected between the pair ofinput terminals and/or the pair of output terminals and comprising twoseries connections respectively formed by an inverter and ashort-sectioned inverter connected antiparallely between said inputterminals or said output terminals; each of said inverters beingconstituted by at least one MOS, CMOS or BiCMOS transistor having agate, drain, source and a channel region between said drain and source;including the following step: selecting the channel region dimensions ofthe transistors of the gyrator core section and/or the common modefeedback section such that the following relationship is fulfilled:

g*C≧g_(m)*c_(m) where: g: effective conductive loading of the gyratorcore section terminals; C: effective capacitive loading of the gyratorcore section terminals; g_(m): effective gyrating constant of thegyrator core section; and c_(m): effective transcapacitance of thegyrator core section.

Furthermore, the object is solved by a method for making a filtercircuit consisting of at least one filter stage FSTi which comprises thefollowing steps:

providing S1 said at least one filter stage FSTi with a gyrator coresection GCi having four inverters I1, I12, I22, I21 mutually connectedin a feedback loop between a pair of input terminals i_1, i_2 and a pairof output terminals o_1, o_2; wherein the inverters are arranged as adifferential transconductor configuration, such that a first and secondinverter I11, I21 are respectively provided between the first input andfirst output terminal i_1; o_2 and the second input terminal and thesecond output terminal i_2; o_2; each of said inverters beingconstituted by at least one MOS, CMOS or BiCMOS transistor having a gateG, drain D, source S and a channel region CH between said drain D andsource S;

selecting S4 the general region dimensions CL, CB of the transistors ofthe gyrator core section such that the following relationship isfulfilled: g*C≧g_(m)*c_(m)

where: g: effective conductive loading of the gyrator core sectionterminals; C: effective capacitive loading of the gyrator core sectionterminals; g_(m): effective gyrating constant of the gyrator coresection; and c_(m): effective transcapacitance of the gyrator coresection.

Furthermore, this object is solved by a filter circuit consisting of atleast one filter stage FSTi, which comprises:

at least one filter stage FSTi with a gyrator core section GCi havingfour inverters I1, I12, I22, I21 mutually connected in a feedback loopbetween a pair of input terminals i_1; i_2 and a pair of outputterminals o_1; o_2; wherein the inverters are arranged as a differentialtransconductor configuration, such that a first and second inverter I11,I21 are respectively provided between the first input and first outputterminal i_1; o_1 and the second input terminal and the second outputterminal i_2; o_2; each of said inverters being constituted by at leastone MOS, CMOS or BiCMOS transistor having a gate G, drain D, source Sand a channel region CH between said drain D and source S; the generalregion dimensions CL, CB of the transistors of the gyrator core sectionbeing selected such that the following relationship is fulfilled:g*C≧g_(m)*c_(m)

where: g: effective conductive loading of the gyrator core sectionterminals; C: effective capacitive loading of the gyrator core sectionterminals; g_(m): effective gyrating constant of the gyrator coresection; and c_(m): effective transcapacitance of the gyrator coresection. According to the invention the problem was discovered that thechannel delay of the transistor structures used in the gyrator circuitsactually make the circuit unstable and causes the deviation from theactual filter characteristic from the expected theoretical filtercharacteristic. According to the invention it was realized that thenon-quasi-static behavior of the channel charge does indeed add aparasitic pole in the transconductance of the device. This extra pole ordelay makes the gyrator unstable and therefore must be designedproperly. Whenever the channel delay becomes significant, it istherefore necessary to design the channel region dimension such thatg*C≧g_(m)*c_(m) is fulfilled. It is also not necessary to add Q-tuningto the ballast inverters in the common mode feedback network. If thechannel region dimensions of the MOS transistors are designed to fulfillthis condition also higher-order filters with excellent filtercharacteristics can be provided.

According to a first aspect of the invention the channel regiondimensions are changed differently in the gyrator core section and insaid common mode feedback section. The channel region dimensions of thecommon mode feedback section transistors can be kept constant and thechannel region length of the gyrator core section can be reduced wherebythe transadmittance of the respective transistor is changed. Thus, thedevices are shortened such that the open-circuit voltage gain of thedevices is low enough not to cause instability.

According to a second aspect of the invention the channel regiondimensions of the common mode feedback section transistors are keptconstant and the channel region length and the channel region width ofthe gyrator core section is reduced wherein the transmittance of therespective transistor is kept constant such that the resonance frequencyof the core section {overscore (ω)}_(Tcore) is larger than the resonancefrequency of the filter circuit {overscore (ω)}_(Ofilter). Therefore,the gyrator-core devices can be scaled down such that their delaybecomes insignificant.

According to a third aspect of the invention, when the channel regiondimensions have been designed such that the overall filter fulfillsg*C≧g_(m)*c_(m), additional ballast inverters can be added to the commonmode feedback section. Essentially, the channel region width of thetransistors of the common mode ballast inverters in the common modefeedback section is increased. That is, the CM ballast inverter channelregion is widened and one must discriminate here between the CM ballastinverter connected to one terminal (CMI2 and CMO2) whose width isactually increased and the CM inverters connected between terminals(CMI1, CMO1) whose width can be kept constant.

Preferably, the channel length of the CM inverters (CMI1 and/or CMO1)can be made longer (even though this may be inferior to widening CMx2)as this will create a similar gain imbalance.

According to a fourth aspect of the invention, the aforementionedstability criteria and further stability criteria discussed hereinaftercan be employed for a filter circuit which is formed by a differentialtransconductor configuration in a feedback loop without additionalcommon mode feedback sections.

The above-mentioned schemes are applicable to symmetrical andasymmetrical realizations of the inverters.

Further advantageous embodiments and improvements of the invention canbe taken from the dependent claims. Furthermore, it should be noted thatthe invention is not restricted to the embodiments and examplesdescribed hereinafter and that further embodiments of the invention maycomprise features which have been described separately in the claims andin the description. Hereinafter, embodiments of the invention will bedescribed with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a typical filter circuit comprising a number of filterstages FST1 . . . FSTi according to the prior art;

FIG. 2 shows an equivalent circuit diagram of a gyrator;

FIG. 3 shows a differential signal type gyrator circuit comprising acore section GCi and common mode feedback sections CMIi, CMOi accordingto the prior art;

FIG. 4 shows a CMOS transistor construction of an inverter used in FIG.3;

FIG. 5a shows an equivalent circuit diagram of differentialtransconductor;

FIG. 5b shows a differential transconductor realization of the gyratorcore section GCi shown in FIG. 3; and

FIG. 6 shows a flow chart of the design method according to theinvention.

It should be noted that in the drawings the same or similar referencenumerals are used and that the filter circuit according to the inventioncan use any gyrator core constitution realized by MOS, CMOS, BiCMOS orbipolar transistors. The invention is also not restricted to thedifferential transconductor structure of FIG. 5b or the construction ofFIG. 3.

PRINCIPLE OF THE INVENTION

Hereinafter, the principle of the invention will be described withrespect to a stability analysis of the Nauta cell shown in FIG. 3.However, as explained above, a similar stability analysis will hold forFIG. 5b. Furthermore, the stability analysis is also not restricted toMOS, CMOS or BiCMOS gyrator construction and also a bipolar transistorconstruction of the gyrator can be subjected to the stability analysis.As such the bipolar transistor does not comprise a channel, however,there is a delay associated with the base transport. Thus, in bothtechnologies there is a base or gate delay, i.e. the drain/collectorcurrent does not react immediately to a gate/base terminal voltagechange due to this delay. An extra delay then depends on the MOS channellength or the bipolar base spreading resistance and transit time.

The inventors considered several issues when designing filter gyratorsbased on the Nauta cell. In particular, the gyrator stability Q-valueand the matching properties and noise was investigated. Matching is notsuch an important aspect but is in general improved when the devicedimensions increase. Noise has already been described in theafore-mentioned IEEE paper.

Essentially, the principle of the present invention is based on the ideathat a stability analysis is carried out for the Nauta cell gyratorstructure of FIG. 3 including the channel delay, i.e. the channeldimensions of the transistors used for realizing the inverters andshort-sectioned inverters. The admittance matrix of the configuration inFIG. 3 can be derived as follows: $\begin{matrix}{{Y_{inv} = \begin{pmatrix}{{yi} + {yf}} & {- {yf}} \\{{ym} - {yf}} & {{yo} + {yf}}\end{pmatrix}},} & (1)\end{matrix}$

Herein y_(i) is the input admittance, y₀ is the output admittance, y_(f)is the transadmittance from output to input and y_(m) is thetransadmittance from input to output. That is, the complete admittanceY_(short)=(y_(i)+y₀+y_(m)). The admittance matrix Y_(core) of thegyrator core section can be derived as follows: $\begin{matrix}{{Y_{core} = \begin{pmatrix}{{yl} + {yf}} & {- {yf}} & \quad & {{ym} - {yf}} \\{{ym} - {yf}} & {{yl} + {yf}} & {- {yf}} & \quad \\\quad & {{ym} - {yf}} & {{yl} + {yf}} & {- {yf}} \\{- {yf}} & \quad & {{ym} - {yf}} & {{yl} + {yf}}\end{pmatrix}},} & (2)\end{matrix}$

The admittance matrix of the common mode feedback block can be definedas Y_(CM): $\begin{matrix}{{Y_{CM} = \begin{pmatrix}{{2{yl}} + {ym}} & \quad & {{ym} - {2{yf}}} & \quad \\\quad & {{2{yl}} + {ym}} & \quad & {{ym} - {2{yf}}} \\{{ym} - {2{yf}}} & \quad & {{2{yl}} + {ym}} & \quad \\\quad & {{ym} - {2{yf}}} & \quad & {{2{yl}} + {ym}}\end{pmatrix}},} & (3)\end{matrix}$

In both equations yl=yi+yf+yo. Thus, a complete gyrator admittancematrix Y_(gyr) is derived by adding the two admittance matrixesY_(core), Y_(CM) as follows: $\begin{matrix}{Y_{gyr} = \begin{pmatrix}{\quad {{3{yl}} + {ym} + {yf}}} & {- {yf}} & {{ym} - {2{yf}}} & {{ym} - {yf}} \\{{ym} - {yf}} & {{3{yl}} + {ym} + {yf}} & {- {yf}} & {{ym} - {2{yf}}} \\{{ym} - {2{yf}}} & {{ym} - {yf}} & {{3{yl}} + {ym} + {yf}} & {- {yf}} \\{- {yf}} & {{ym} - {2{yf}}} & {{ym} - {yf}} & {{3{yl}} + {ym} + {yf}}\end{pmatrix}} & (4)\end{matrix}$

Two kinds of stability problems can occur in the Nauta cell. Firstly,when oscillating in the common mode the inputs and outputs are in phaseand for example v_(i1)=v_(i2) (where V_(i1) and V_(i2) denode thevoltages between the inputs i_1, i_2 versus ground). The common modefeedback network CNIi by Nauta ensures that this cannot happen since theloop gain is limited to ½ for common mode signals. Therefore, the onlystability problem which needs to be analyzed is for the differentialcase where the following relations apply for the differential signals:

v_(i1)=−v_(i2)

v_(o1)=−v_(o2)

i_(i1)=−i_(i2)

i_(o1)=−i_(o2)  (5)

wherein v_(i1), v_(i2) and v_(o1 and v) _(o2) are the respectivevoltages at the input and output terminals i_1; i_2 and o_1; o_2 andi_(i1), i_(i2) and i_(o1) and i_(o2) are the respective currents at theinput and output terminals.

Equations (4), (5) can be used for carrying out a stability analysis forthe general case where it is not necessarily assumed that all inverters(transistors) are identical. That is, the matrix elements of Y_(gyr)contain the respective values of individual realizations of theinverters.

When the differential signal assumptions of equation (5) are used, thenit is possible to simplify the problem by deleting the last two rows andsubtract the last two columns from the first two of equation (4). Thisresults in a reduced admittance matrix for the differential operation ofthe Nauta gyrator cell that is easier to analyse. Thus, equation (4) canbe reduced to: $\begin{matrix}{{Y_{gyr} = \begin{pmatrix}{{3\left( {{yi} + {2{yf}} + {yo}} \right)} + {\Delta \quad {ym}}} & {- {ym}} \\{ym} & {{3\left( {{yi} + {2{yf}} + {yo}} \right)} + {\Delta \quad {ym}}}\end{pmatrix}},} & (6)\end{matrix}$

This equation can be further simplified if Y_(l)=3(Y_(i)+2Y_(f)=Y₀) isdefined. This leads to the following equation: $\begin{matrix}{{Y_{gyr} = \begin{pmatrix}{{Yl} + {\Delta \quad {ym}}} & {- {ym}} \\{ym} & {{Yl} + {\Delta \quad {ym}}}\end{pmatrix}},} & (7)\end{matrix}$

Δ_(Ym) represents the difference between the transadmittances andrepresents the gain imbalance in the common-mode feedback inverters(typically some 1-10% of y_(m)).

In equation (7) for the gyrator admittance matrix Y_(gyr) the importanttransadmittance y_(m) occurs. Depending on the realization of therespective inverters (CMOS, MOS, BiMOS or bipolar) y_(m) constitutes aspecific delay of the transistor. As explained above, in the MOS casey_(m) is linked to the channel region dimensions or the channel delayand in the bipolar realization y_(m) corresponds to the base delay.Thus, one can say that y_(m) represents a contribution which is due tothe delay of the collector/emitter current with respect to the gate/basecurrent. Hereinafter, a special case of a MOS transistor will beconsidered, however, similar considerations hold for the derivation incase of bipolar transistors.

When the Nauta gyrator circuit is implemented by MOS transistors, it canbe assumed that y_(i)=C_(gs), y_(f)=C_(gd) and y₀=gd. Herein, C_(gs)represents the gain/source capacity C_(gs), C_(gd) represents thegain/drain capacities and g_(d) represents the output conductance of thetransistor. If the load is dominated by external high-Q capacitors C₀(i.e. the total effective capacitance between the gyrator core terminalsdue to the common mode feedback section and/or additional externalcapacitances, this capacitance has to be added to the diagonal elementsof equation (7). If Y_(l) is expanded as Y_(l)=s*C+g, then the followingvalues are obtained for Y_(l):

C=C ₀+3C _(gs)+6C _(gd)  (8.1);

g=3g _(D)  (8.2).

If the total effective capacitance is dominated by the external load,then C≈C₀ is satisfied.

At this stage it should be noted that also other approximations fory_(i) can be used, e.g. for a CMOS realization one has to puty_(i)=C_(gs)N+C_(gsP). A skilled person can make derivations fordifferent types of transistors on the basis of the teachings containedherein.

The only missing parameter for the stability analysis is the MOStransadmittance y_(m). In the afore-mentioned IEEE paper the MOStransadmittance y_(m) has been assumed to be purely conductive and itwas assumed that a stable system can always be obtained. That is, in theconventional filters the channel delay, which does add a parasitic polein the transconductance of the device, has not been considered. However,as will be seen below, this extra pole or delay makes the gyratorunstable if not designed properly. Only under special circumstances, ifthe gyrator is for example loaded with resistive filter terminations,the entire circuit may be stable even though the gyrator core itself isunstable. This is one reason why simpler filters as given in the IEEEpaper actually do not exhibit any stability problem whilst more complexones (higher-order) do not work.

According to the invention it has been realized that y_(m) is aninfluential parameter in the stability analysis and that it is notjustified to assume it to be purely conductive. Therefore, according tothe principle of the invention the non-quasi-static channel delay forthe non-quasi-static MOS transadmittance y_(m) (or a correspondingfeature in the bipolar transistor realization) is modeled as:$\begin{matrix}{{ym} = {{gm}^{e^{{s \cdot \tau}\quad {gm}}} \approx \frac{g}{1 + {{s \cdot \tau}\quad {gm}}} \approx {{gm} - {s \cdot c_{m^{\prime}}}}}} & (9)\end{matrix}$

where τ_(gm)=2/Eω_(T) and c_(m)=2C_(gs)/E with E≈5. The values of y_(m),τ_(gm) and E are known from standard MOS transistor technology handbooks(see for example Y P. Tsvidis “Operation and modeling of the MOStransistor, McGraw-Hill New York, 1988”).

As can be seen from equation (9), the MOS transadmittance y_(m) isactually a pure delay (a circle in the S-plane) and this can beapproximated either by using a pole approximation or by a righthalf-plane zero. Since the exact delay equation (the first term inequation (9)) leads to transcendental equations when solving thecharacteristic equations, hereinafter, pole and zero approximations areused. It can be shown that the pole and zero approximations of the MOStransadmittance y₀ lead to the same phase lag which is important for thestability analysis. The zero approximation gives /y_(m)/ a high-passcharacteristic and a pole approximation leads to a low-passcharacteristic. The pole approximation is more realistic but is morecomplex to analyze. Therefore, hereinafter, the zero approximation isused for deriving the stability criterion according to the invention.

Using the zero approximation y_(m)=g_(m)−s*c_(m), the characteristicequation of equation (7) can be derived as follows:

Δ=(Yl+Δym)² +y ² m=s ²·(C ² +c ² m)+2s·(g·C−gm·c _(m))+g ² +g ² m,  (10)

where Δy_(m) has been assumed to be negligible, i.e. the differencebetween the transfer admittances in the common-mode feedback invertershas been assumed to be zero. That is, the above-mentioned equation (10)has been derived on the basis of using differential signals, using azero approximation and using identical transistors in the common-modefeedback circuit in the gyrator core section.

A sufficient and necessary requirement for equation (10) to be stable isthat all coefficients in the s-polynomial are positive. Then, thestability criterion

g·C>gm·cm,  (11)

may be derived. It must be noted that this stability criterion is novelover the IEEE document since equation (11) has been derived by assumingthat the channel delay (base delay in a bipolar transistor) as anadditional delay must not be neglected.

In this equation g and c as well as g_(m) and c_(m) correspond to thevalues obtained in equation (8.1), (8.2) and (9). In particular, a zeroapproximation for y_(m) has been used.

It should be noted that the pole approximation y_(m)=g_(m)/(1+S*τ_(gm))leads to the same stability criterion when deriving a characteristicequation for the characteristic equation (7). Therefore, there is nonecessity to explicitly explain the pole approximation here.

The important conclusion is that equation (11) gives a specificrelationship which must be fulfilled in order that the gyrator coresection is stable independent of the frequency and independent of thecomplexity of the inverter realizations.

Although the principle of the invention has been described above withreference to the symmetric case where g, C, g_(m) and c_(m) aredescribed by the above equations (8.1), (8.2) and (9), it may be notedthat even for the asymmetrical case a similar relationship is fulfilled.Therefore, independent as to whether or not all transistors areidentical, a general relationship like equation (11) is fulfilled.

Thus, in the general case g will be the effective conductive loading ofthe gyrator core section terminal, C will represent the effectivecapacitive loading of the gyrator core section terminals, g_(m) will bethe effective gyration constant of the gyrator core section, and c_(m)will be the effective transcapacitance of the gyrator core section.Therefore, the above relationship (11) is not restricted to the specialsymmetrical case.

However, for the symmetrical and for the asymmetrical case the importantrealization of the invention is the same, namely that thenon-quasi-static channel delay of the equation (9) should not beneglected for the stability analysis and should be selected such thatequation (11) is satisfied. As shown with equation (9) g_(m) and c_(m)respectively describe the effective gyration constant or the resistivepart of the MOS transadmittance y_(m) and the effective transcapacitanceof the gyrator core section or the capacitive part of the MOStransadmittance y_(m).

According to the invention the channel region dimensions of thetransistors of the gyrator core section and/or the common-mode feedbacksection must therefore be selected such that g, C and g_(m), c_(m)fulfill equation (11).

Various embodiments of the invention can be designed on the basis ofthis realization.

Comparison with a Design According To Nauta

As explained above, in the IEEE journal prior art document and thecorresponding PhD thesis the channel delay (e.g. equation (9)) was notconsidered and the stability criterion (11) was not used.

Essentially, Nauta suggested to add additional Q-tuning loops in thecommon-mode feedback section, together with keeping the devices as smallas possible. That is, Nauta suggested to shorten all devices in thecommon-mode feedback circuit and the gyrator core section and to add anexternal capacitance. In terms of equation (11) this would lead to anincrease of g and a reduction of c_(m). Therefore, following Nauta'sdesign rule the condition (11) was fulfilled but required externalcapacitances and caused more mismatch (i.e. coefficient spread) and onlyworks when the ω₀ of the filter is much smaller than ωT. Furthermore,smaller filters with terminations (additional capacitance) also assume ahigh g due to the terminations. However, this does not work for complexfilters.

Nauta did not consider that the channel region dimensions must beoptimized with respect to mismatch and stability simultaneously, and hisdesign rule did not indicate that the channel region dimensions shouldbe selected such that equation (11) is satisfied.

That is, Nauta did a quick analysis of the channel delay and concludedthat it was not a problem since one would use short channels anyway.That is, Nauta only considered short channels (i.e. close to thetechnology minimum feature size which will result in a delay that isless than 1/fT). Using such short channels a device mismatch will, formore complex filters, cause filters with such short channels to have alarge variation in transfer characteristics (i.e. they will not begenerally useful).

The following embodiments can be devised on the basis of the equation(11) having realized that the channel delay (or the channel regiondimensions such as width and length) should be taken into account.

First Embodiment

The first embodiment of the invention relates to the filter circuitsshown in FIG. 3 consisting of at least one filter stage FSTi whichcomprises a filter circuit consisting of at least one filter stage FSTiwhich comprises: a gyrator core section GCi having four inverters GI1i-GI4 i mutually connected in a loop configuration between a pair ofinput terminals i_1; i_2 and a pair of output terminals o_1; o_2; atleast one common mode feedback section CMIi, CMI connected between thepair of input terminals and/or the pair of output terminals andcomprising two series connections respectively formed by an inverterCMI1, CMO1 and a short-sectioned inverter CMI2, CMO2 connectedantiparallely between said input terminals or said output terminals;each of said inverters being constituted by at least one MOS, CMOS orBiCMOS transistor having a gate G, drain D, source S and a channelregion CH between said drain D and source S; wherein the channel regiondimensions CL, CW of the transistors of the gyrator core section and/orthe common mode feedback section are selected such that the followingrelationship is fulfilled:

g*C>g_(m)*c_(m)  (16.1)

where:

g: effective conductive loading of the gyrator core section terminals;

C: effective capacitive loading of the gyrator core section terminals;

g_(m): effective gyrating constant of the gyrator core section; and

c_(m): effective transcapacitance of the gyrator core section;

The first embodiment is based on the shortening of the core devices withregard to the common-mode feedback devices. Therefore, the open-circuitvoltage gain of the devices is low enough not to cause an instability.That is, according to the first aspect the channel region dimensions areselected to be different in said gyrator core section and in saidcommon-mode feedback section (whilst Nauta had suggested to use the samesize for all devices).

The shortening of the core devices leads to an increase of g and asubstantial reduction of c_(m). Therefore, the channel region dimensionsof the common-mode feedback section transistors are kept constant andthe channel region length of the gyrator core section devices is reducedwherein the transadmittance y_(m) of the respective transistors ischanged. This stabilizes the filter/gyrator core but has some mismatchproblems. On the other hand, this design strategy already removes theneed of a Q-tuning loop as in the IEEE journal prior art. This isespecially important as Q-tuning does not work the way originallyproposed, at least not for complex filters. With the proposed designstrategy according to the first embodiment a Q-tuning loop will workbetter but will be more or less redundant.

Second Embodiment

According to a second embodiment of the invention the equation (11) isfulfilled by keeping the channel region dimensions of the common modefeedback section transistors constant and by reducing the channel regionlength as well as the channel region width of the gyrator core sectiontransistors, wherein the transadmittance of the respective transistor iskept constant such that the resonance frequency of the core sectionω_(Tcore) is larger than the resonance frequency of the filter circuitω_(0filter). The second embodiment leads to a filter circuit which isstill sensitive with respect to the transistor output conductance g_(d)as does a filter circuit according to the first embodiment.

However, since according to the second embodiment the gyrator coredevices (transistors) are scaled down, the matching with respect to theexternal capacitance is maintained. In the second embodiment c_(m) istherefore reduced also substantially since the length as well as thewidth of the channel region is reduced in order to fulfill equation(11).

Third Embodiment

According to a third embodiment of the invention the transistors of thegyrator core section are kept constant with respect to their channelregion length and the channel region width of the common mode ballastinverters CMI2, CMO2 of the common mode feedback section transistors isincreased. Keeping the core transistors constant and increasing thechannel width of the common mode feedback transistors leads to asubstantial increase in g. The increasing of the width of the commonmode feedback section transistors can be achieved by adding in parallelto the inverters, e.g. the ballast inverters CMI2, CMO2, in the commonmode feedback section ballast inverters.

The criterion according to the third embodiment is the most attractiveone as it is only sensitive to fundamental device characteristics(forward gain, transit frequency and channel delay relative to thetransit frequency) which are better characterized, controlled andmodeled than for example the transconductance g_(d) from which gdepends.

The design solution is then to choose one of the above schemes andindividually tune each filter gyrator or integrator loop with allexternal capacitors added for maximum stable Q. The resulting circuitwill have near ideal transfer characteristics and low sensitivity todevice variations since an additional channel delay has been consideredin the design equation (11).

Preferably, the channel length of the CM inverters (CM1 and/or Cmo1) canbe made longer (even though this may be inferior to widening CMx2) asthis will create a similar gain imbalance.

Fourth Embodiment

As explained above, the core idea of the present invention is toincorporate the channel delay in the stability analysis of equation(11). Therefore, one can say that the core principle of the invention isto individually dimension the channel of the gyrator MOS transistorsand/or integrators to cancel out the effects of the channel delay andthe limited open-circuit voltage gain which could lead to equation (11)not being fulfilled.

As shown in FIG. 6, a flow chart for designing a stable filter circuitaccording to the invention comprises steps S1-S4. In step S1 the filtercircuit, more precisely the individual filter stage FSTi is providedwith the gyrator core section transistors. In step S2 at least onecommon mode feedback section is added at the input or at the outputterminals. By a contrast to the design of Nauta, it can be assumed atthis stage that equation (11) is not fulfilled in step S3.

The idea of the invention is now to select in step S4 the channel regiondimensions of the transistors of the gyrator core section and/or thecommon mode feedback section such that the equation (11) is satisfied.

The selection of the channel dimensions can then be performed in step S4according to the first, second and third embodiment individually.

Fifth Embodiment

It is also possible to combine the first and the third embodiment. Thatis, the channel region length of the gyrator core section can be reducedwherein the transadmittance of the respective transistor is changed andat the same time the channel region width of the common mode feedbacksection is increased according to the third embodiment, until equation(11) is satisfied.

It is also possible to combine the second and the third embodiment. Thatis, the channel region length and the channel region width of thegyrator core section transistors is reduced wherein the transadmittanceof the respective transistor is kept constant whilst the channel regionwidth of the common mode feedback section is increased.

Furthermore, it is possible that all transistors in the common modefeedback section and the gyrator core section are identical or it ispossible that all transistors in the common mode feedback section andthe gyrator core section are different. If it is assumed that alltransistors in the common mode feedback section and the gyrator coresection are identical then the transistors of each of the inverterscomprise a transistor structure having a gate/source capacity C_(gs), agate/drain capacity C_(gd), an output conductance g_(d) and atransadmittance y_(m) consisting of a resistive part g_(m) and acapacitive part c_(m) wherein the values in equation (11) are definedas:

C=C ₀+3C _(gs)+6C _(gd)  (8.1)

g=3g _(D)  (8.2).

wherein C₀ is the total effective capacitance between the gyrator coreterminals due to the common mode feedback section and/or additionalexternal capacitances. If symmetrical signals are used C₀ corresponds tothe total effective capacity between the input or output terminals.

Furthermore, it should be noted that all transistors can be operated insaturation and that the filter circuit may be a differential signal typefilter circuit. Furthermore, it should be noted that any of the circuitconfigurations described in FIG. 5a and FIG. 5b, i.e. a differentialtransconductor realization of the gyrators is possible. Therefore, whathas been said for the design of the Nauta cell structure in FIG. 3equally well applies to the structure in FIG. 5b.

Sixth Embodiment

Furthermore, a special embodiment of the invention is when a channeldelay and the gyrator open-circuit voltage gain cancel each other, i.e.:

g*C=g _(m) *c _(m)  (12).

In this case the resulting Q is very high (infinite in the nominal case)enabling high Q circuits with low-Q active devices. For the specialrelationship (12) less external terminations maximize the filter Qwhilst setting g*C>>g_(m)*c_(m) results in a very low Q.

Seventh Embodiment

As explained above, the requirement to fulfill equation (11) can resultin making c_(m) sufficiently small by making the gyrator-core invertertransistors shorter than the common-mode feedback ones (i.e. ω_(t)>>ω₀)or by loading the cell resistively (i.e. increase g) by adding ballastinverters (something that Nauta did with the Q-control).

Using equation (11) and assuming typical long-channel device parameters:$\begin{matrix}{{\frac{ym}{yo} = {A_{0} = 300}}{{\frac{yi}{cm} = {\frac{Cgs}{cm} = 2.5}},}} & (13)\end{matrix}$

 C=C₀

the following special relationship holds for c_(m): $\begin{matrix}{{{cm} = {\frac{2C_{gsgyr}}{ɛ} < {\frac{g}{gm}C_{o}} \approx \frac{3C_{o}}{A_{0}} \approx {\frac{C_{o}}{100}.}}},} & (14)\end{matrix}$

By making the gyrator-core devices shorter the ω^(t) (resonancefrequency) of the core devices is increased and therefore the c_(m) isdecreased with the same amount as ωt is increased. Since typicallyc_(m)=2.5*C_(gs) the following relationship can be obtained:$\begin{matrix}{{C_{gsgyr} < \frac{C_{o}}{40}},} & (15)\end{matrix}$

When shortening the gyrator-core devices their width has to be narrowedwith a similar amount to preserve g_(m) to be constant. This scaling orshortening of the devices will increase g_(d) proportionally and theresistive losses in the gyrator increases making equation (15) overlyconservative. However, equations (14) and (15) can be used when assumingtypical long-channel device parameters of equation (13). C₀ in the aboveequations (13)-(15) is the total effective capacitance between thegyrator core terminals.

Eight Embodiment

The above relationships (13)-(15) were derived on the basis of the zeromodel approximation for the stability equation (11). As explained above,the pole model approximation yields the same result. These results areapplicable for MOS transistors and model the channel delay by a zero ora pole approximation for the case of selecting identical transistors inthe common mode feedback section and the core section.

However, also the MOS transistor input admittance makes an influence onthe stability criteria. Due to matching considerations the MOS devicesmay be longer than their minimum length and hence ω_(t) may beapproaching ω₀ of the filter why non-quasi-static effects becomesignificant in this case.

When the gyrator is tuned by C_(gs) and g_(m) (i.e. the reactive load isdue to y_(i), and others as in equation (6)) the MOS transistor willoperate closely to ω_(t) and it is necessary to include non-quasi-staticcharging effects not only in the transadmittance expression but also inthe input admittance y_(i). For minimum-length devices the gateresistance also becomes a factor but in low-frequency gyrator designthis is not a problem.

The output admittance is often modeled as a conductance g_(d) withsufficient accuracy but should otherwise be g_(d)/(1+s*τ_(gm)) accordingto the aforementioned MOS transistor handbook by Y. P. Tsvidis of 1988.

The distributed and lossy nature of the channel adds an effectiveconductance g_(ch)=εg_(m)≈5g_(m) in series to C_(gs). The channel chargethen exhibits a low-pass character with time constantτ_(gs)=C_(gs)/g_(ch)≈⅕ω_(t). The transconductance time constant is twiceτ_(gs) such that τ_(gm)˜2/(5ω_(t)). Often the effects due to τ_(gs) andτ_(gm) are however neglected in simulation models and one has to be verycareful when interpreting simulation results.

By adding the resistive component in the input admittance and byinserting typical MOS parameters as above, equation (6) is reformulatedas $\begin{matrix}{Y_{gyr} = \left( \begin{matrix}{3\left( {\frac{s \cdot C_{gs}}{1 + {{s \cdot \tau}\quad {gs}}} + {2C_{gd}} + \frac{gd}{1 + {{s \cdot \tau}\quad {gm}}}} \right)} & {- \frac{gm}{1 + {{s \cdot \tau}\quad {gm}}}} \\\frac{gm}{1 + {{s \cdot \tau}\quad {gm}}} & {3\left( {\frac{s \cdot C_{gs}}{1 + {{s \cdot \tau}\quad {gs}}} + {2C_{gd}} + \frac{gd}{1 + {{s \cdot \tau}\quad {gm}}}} \right)}\end{matrix}\quad \right)} & (16)\end{matrix}$

where it was assumed that Δgm can be neglected. Further C_(gd) istypically insignificant compared with C_(gs). Thus, equation (16) can besimplified and using the fact that τ_(gm)=2τ_(gs) the characteristicequation of equation (16) can be derived as $\begin{matrix}\begin{matrix}\begin{matrix}{{Y_{gyr}} = \quad {{\begin{matrix}\frac{3}{1 + {{s \cdot \tau}\quad {gm}}} & 0 \\0 & \frac{3}{1 + {{s \cdot \tau}\quad {gm}}}\end{matrix}} \cdot}} \\{{\quad \quad}{\begin{matrix}{{{s \cdot C_{gs}}\quad \frac{1 + {{s \cdot \tau}\quad {gm}}}{1 + {{s \cdot \tau}\quad {gs}}}} + g_{d}} & {- \frac{gm}{3}} \\\frac{gm}{3} & {{{s \cdot C_{gs}}\quad \frac{1 + {{s \cdot \tau}\quad {gm}}}{1 + {{s \cdot \tau}\quad {gs}}}} + g_{d}}\end{matrix}}} \\{\approx \quad {\left( \frac{3}{1 + {{s \cdot \tau}\quad {gs}}} \right)^{2} \cdot}}\end{matrix} \\{{{\begin{matrix}{{s \cdot {C_{gs}\left( {1 + {s \cdot \left( {{\tau \quad {gm}} - {\tau \quad {gs}}} \right)}} \right)}} + g_{d}} & {- \frac{gm}{3}} \\\frac{gm}{3} & {{s \cdot {C_{gs}\left( {1 + {s \cdot \left( {{\tau \quad {gm}} - {\tau \quad {gs}}} \right)}} \right)}} + g_{d}}\end{matrix}} \approx}\quad} \\{\quad {\left( \frac{3}{1 + {{s \cdot \tau}\quad {gs}}} \right)^{2} \cdot}} \\{{\begin{matrix}{{s \cdot {C_{gs}\left( {1 + {{s \cdot \tau}\quad {gs}}} \right)}} + g_{d}} & {- \frac{gm}{3}} \\\frac{gm}{3} & {{s \cdot {C_{gs}\left( {1 + {{s \cdot \tau}\quad {gs}}} \right)}} + g_{d}}\end{matrix}} = 0.}\end{matrix} & \text{(17.1)}\end{matrix}$

The stability condition—when expanding the last determinant of equation(17.1) since only right-plane poles need to be examined—is then:$\begin{matrix}{{{4{C_{gs}^{6}\left( {\frac{g_{d}}{ɛ\quad {gm}} - \left( \frac{g_{d}}{ɛ\quad {gm}} \right)^{2} - \frac{g_{d}^{2} + \frac{g_{m}^{2}}{9}}{ɛ^{2}g_{m}^{2}}} \right)}} \approx {4{C_{gs}^{6}\left( {\frac{1}{ɛ\quad A_{0}} - \left( \frac{1}{ɛ\quad A_{0}} \right)^{2} - \frac{1}{9ɛ^{2}}} \right)}} > 0},} & (17.2)\end{matrix}$

with the solution (under the assumption A₀>>1):

A ₀<9ε≈45.  (18)

To meet the above criterion the gyrator devices can be scaled down insize as was already explained above with respect to the secondembodiment. If only the core transistors are resized they have to bescaled more than equation (18) as the g_(d) term corresponds to the sumof all output conductances.

As explained above with respect to the eight embodiment which includesthe MOS transistor input admittance in the characteristic equation, aspecial relationship (18) holds for designing the channel length in caseof also incorporating the input admittance effects in the stabilityanalysis.

Ninth Embodiment

As explained above with reference to equations (13), (14), the stabilityof the gyrator may be studied with sufficient accuracy by lettingy_(m)=g_(m)−s*c_(m) with c_(m)≈εg_(m)/(2ω_(T))≈C_(gs)/2.5.

When the loading capacitance (C₀ of equation 13) is dominated by anexternal capacitor with negligible losses the stability condition ofequation (18) or $\begin{matrix}{{\sum C_{{gs}\quad {gyr}}} < \frac{3C_{0}ɛ}{2A_{0}} \approx \frac{C_{0}}{40}} & (19)\end{matrix}$

is used. If the loading is dominated by lossy gate capacitances equation(18) or $\begin{matrix}{A_{0} = {\frac{g_{mN} + g_{mP}}{g_{dN} + g_{dP}} < 45.}} & (20)\end{matrix}$

can be used as a stability criterion. The two stability conditions (19,20) can be compared by inserting C₀=3C_(gs gyr),A₀=g_(d)/g_(m)=g/3/g_(m),c_(m)=2C_(gs)/ε in equation (14) yielding$\begin{matrix}{{{2\frac{C_{gs}}{ɛ}} < {9\frac{g_{d}}{g_{m}}C_{gs}} \equiv A_{0} < {\frac{9}{2}ɛ}},} & (21)\end{matrix}$

which is the same as equation (18) less a factor of two. By adding C₀ tothe diagonal of equation (16) it can be seen that in (17.1) C_(gs) getsmultiplied by s*τ_(gs) while C₀ gets multiplied by s*τ_(gm). Sinceτ_(gm)≈2T_(gs) the difference between (21) and (18) is explained. Extraphase margin is, thus, introduced by g_(ch) in series with C_(gs) whichmakes the gyrator with internal load more stable. This change in phasemargin was never mentioned by Nauta.

Adding an external capacitor seems to lower the stability margin by afactor of two. At the same time, however, the devices have to be scaledin size, or the resonance frequency will not be preserved, and theincreased loading due to a higher g_(d) (i.e. lower A₀) stabilizes theloop.

For the loop to be stable g*C>g_(m)*c_(m) has to be fulfilled. Asexplained above, this constraint may be fulfilled by either reducingc_(m) by scaling the gyration devices (i.e. by shrinking their lengthand width), or by increasing g by creating an imbalance in Δy_(m). Bothschemes are good candidates but mismatching the CM feedback such thatg=3g_(d)+αg_(m), where α is some 1-10% limits the dependence on theunreliable and poorly modeled g_(d). Then the stability of the designmainly depends on g_(m) and ε which are relatively stable over processvariations.

When an imbalance is created in the CM feedback it is advantageous to doso via the loading devices (shorted inverters) or the y_(f) terms of (2)and (4) will not be identical and cancellation will not occur.

Tenth Embodiment

A further embodiment of the invention is to include the effects of N-and P-channel device differences. If it is here assumed that the N- andP-channel devices in the common mode feedback circuit and the corecircuit are similar except for the mobility, then the only majordifference between device types is in their f_(T) cut-off frequency. Inthis case the input admittance is defined as follows: $\begin{matrix}\begin{matrix}{y_{i} = \quad {\frac{s \cdot C_{g\quad {SN}}}{1 + {s \cdot \tau_{gsN}}} + \frac{s \cdot C_{gsP}}{1 + {s \cdot \tau_{gsP}}}}} \\{\approx \quad {{s \cdot C_{gsN} \cdot \left( {1 - {s \cdot \tau_{gsN}}} \right)} + {s \cdot C_{gsP} \cdot \left( {1 - {s \cdot \tau_{gsP}}} \right)}}} \\{\approx \quad {{s \cdot \left( {1 + \beta} \right)}{C_{gsN}\left( {1 - {s\frac{1 + \beta^{2}}{1 + \beta}\tau_{gsN}}} \right)}}} \\{{\left. {\approx \quad {s \cdot \left( {1 + \beta} \right)}} \right){C_{gsN}\left( {1 - {s\quad \beta \quad \tau_{gsN}}} \right)}},}\end{matrix} & (22)\end{matrix}$

with β being the ratio of N- and P-device f_(T). The aboveapproximations show that the capacitance will be the sum of thecapacitors but that the time constant will be dominated by the P-devices(since β≈3).

In a similar fashion the gyration (trans-) conductance can be defined as$\begin{matrix}\begin{matrix}{g_{m} = \quad {\frac{g_{mN}}{1 + {s \cdot \tau_{gmN}}} + \frac{g_{mP}}{1 + {s \cdot \tau_{gmP}}}}} \\{\approx \quad {{g_{mN}\left( {1 - {s \cdot \tau_{gmN}}} \right)} + {g_{mP}\left( {1 - {s \cdot \tau_{gmP}}} \right)}}} \\{{\approx \quad {2{g_{m}\left( {1 - {s\quad \tau_{gm}1} + \frac{\beta}{2}} \right)}}},}\end{matrix} & (23)\end{matrix}$

where we have assumed that the transconductances are the same and thatthe time constants differ by the factor β.

To consider N- and P-device differences it, thus, suffices to a firstorder to insert the sum of the C_(gs) and g_(m) contributions in theformulas. The time constants may be approximated to t_(gs)≈τ_(gsP) andt_(gm)≈(τ_(gmN)+T_(gmP)) /2 or with the longest time constant and theaverage time constant, respectively. If these approximate values areinserted into equations (15) and (18) the following conditions forstability are derived:

C _(gS gyr) <C ₀/40/β  (24) $\begin{matrix}{A_{0} < {\frac{9}{2}{ɛ/\beta}}} & (25)\end{matrix}$

Eleventh Embodiment

The above described embodiments state a number of stability criteriawhich can be used for a filter circuit including a gyrator core sectionGCi and at least one common mode feedback section CMIi, CMOi, as forexample shown in FIG. 3. However, a similar stability analysis alsoholds for a filter circuit without a ommon mode feedback section andwith a gyrator core section GCi having a differential transconductorconfiguration as shown in FIG. 5a, FIG. 5b. As shown in FIG. 5b twodifferential transconductors DA1, DA2 are provided in a feedback loop inorder to form the gyrator core GCi. If each transconductor DA1, DA2 isembodied as shown in FIG. 5a, then the circuit in FIG. 5b with fourinverters I11, I12, I22, I21 is formed. As shown in FIG. 5a, eachtransconductor DA is supplied with a bias current Ibias from two currentsources CS1, CS2 which are formed by FET-transistors. Thus, the inputterminals i_1, i_2 are the inputs to the two inverters I1, I2 and theoutput terminals o_1, o_2 are the output terminals of the inverters I1,I2. If the circuit in FIG. 5a is used twice to form the feedback loop,then four current sources CS11, CS12, CS21, CS22 and four inverters I11,I12, I22, I21 are used for forming a gyrator core section GCi of thefilter state. Again, each inverter may be formed by transistors as shownin FIG. 4 with respect to the description of the inverters used in FIG.3.

It may be noted, that in the filter stage in FIG. 5b only one gyratorcore section with four inverters mutually connected in a loopconfiguration between a pair of input terminals i_1, i_2 and a pair ofoutput terminals o_1, o_2 are used in the differential transconductorconfiguration without any additional common mode feedback sections as inFIG. 3. However, of course the circuit in FIG. 5b also has an effectiveconductive loading of the gyrator core section terminals g, an effectivecapacitive loading of the gyrator core section terminals C, an effectivegyrating constant of the gyrator core section g_(m) and an effectivetranscapacitant of the gyrator core section c_(m). However, thestability criteria can at least with respect to the selection of thechannel region dimensions of the transistors of the gyrator core sectioninverters I11, I12, I22, I21 be used as in the stability analysis ofFIG. 3. That is, the channel region dimension of the transistors of thegyrator core section are selected such that the relationshipg*C≧g_(m)*c_(m) is fulfilled. For example, the channel region length ofthe gyrator core section transistors is reduced, wherein thetransadmittance of the respective transistor is changed. All transistorsof the inverters in the gyrator core section can be selected to beidentical. Furthermore, the channel region length and the channel regionwidth of the gyrator core section transistors can be reduced, whereinthe transadmittance of the respective transistor is kept constant. Allother explanation regarding the stability analysis as regards thefulfillment of the aforementioned condition by changing the channelregion dimensions, in particular by shortening the channel length, asexplained above can be used also in FIG. 5b.

Hereinafter, the example circuit of FIG. 5b will be explained with moredetails. The gates of the current source transistors CS11, CS12 areconnected together and their source terminals are connected to apositive power supply V+. Likewise, the gates of the current sourcetransistors CS22, CS12 are connected together and their drains areconnected to ground. The current from the current source CS11 feeds theinverters I12, I22 and the current from the current source CS12 feedsthe inverters I11, I21. The current source CS22 feeds the inverters I12,I22 and the current source CS21 feeds the inverters I11, I21. The inputterminals i_1, i_2 of the gyrator core section GCi are the inputterminals to the inverters I11, I21. The output terminal o_1, o_2 of thegyrator core sections GCi are the output terminals of the inverters I11,I21. The output of the inverter I11 is connected to the input of theinverter I22 whose output is connected to the input of the inverter I21.The output of the inverter I21 is connected to the input of the inverterI12 whose output is connected to the input of the inverter I11. Thus, aninverter is respectively present in the forward path between an inputterminal i_1; i_2 and the respective output terminal o_1; o_2. Therespective output terminal o_1 is coupled back to the second inputterminal i_2 through an inverter an the output terminal o_2 is fed backto the first input terminal i_1 via another inverter. As explainedabove, the stability criterion in equation (11) can also be used forthis type of circuit if the channel region dimensions, in particular thechannel length of the inverter transistors is reduced.

INDUSTRIAL APPLICABILITY

The above embodiments are all based on the central stability equation(11) which can be obtained on the basis of a zero model approximation ora pole model approximation for the MOS transadmittance y_(m).

Furthermore, the input admittance can be included in the characteristicequation according to equation (17.1) leading to the stability criterion(18).

It has also been shown that the stability criteria are the same when theloading capacitance is dominated by an external capacitor and when it isnot dominated. Furthermore, the effects of N- and P-channel devicedifferences are included in a stability criterion according to equations(24), (25).

As explained above, by using the central stability equation (11) and byselecting the channel region dimensions in the core and in the commonmode feedback filters can be obtained which are stable even at highfrequencies and even when realizing higher-order filters.

Furthermore, the invention is not restricted to the above-describedembodiments and further embodiments of the invention can be devised onthe teachings contained therein. In particular, the invention cancomprise embodiments which consist of features which have beenseparately described in the specification and/or claimed in thefollowing claims.

In the claims reference numerals are only used for illustration purposesand do not limit the scope of the invention.

What is claimed is:
 1. A method for making a filter circuit comprisingat least one filter stage, the method comprising: a) providing the atleast one filter stage with a gyrator core section having four invertersmutually connected in a loop configuration between a pair of inputterminals and a pair of output terminals; b) providing at least onecommon mode feedback section, the at least one common mode feedbacksection being connected between at least one said pair of inputterminals and said pair of output terminals and comprising two seriesconnections respectively formed by an inverter and a short-sectionedinverter connected antiparallely between at least one of said inputterminals and said output terminals, each of said inverters including atleast one of a MOS, CMOS, and BiCMOS transistor, the at least one of aMOS, CMOS, and BiCMOS transistor having a gate, drain, source, and achannel region between said drain and source, and c) wherein the channelregion dimensions of the transistors of at least one of the gyrator coresection and the common mode feedback section are selected such that thefollowing relationship is fulfilled: g*C≧g _(m) *c _(m) where:g=effective conductive loading of the gyrator core section terminals;C=effective capacitive loading of the gyrator core section terminals;g_(m)=effective gyrating constant of the gyrator core section; andc_(m)=effective transcapacitance of the gyrator core section.
 2. Themethod according to claim 1, wherein: the channel region dimensions arechanged differently in said gyrator core section and in said common modefeedback section.
 3. The method according to claim 1, wherein: thechannel region dimensions of the common mode feedback sectiontransistors are kept constant and the channel region length of thegyrator core section transistors is reduced; and the transadmittance ofthe respective transistor is changed.
 4. The method according to claim1, wherein: the channel region dimensions of the common mode feedbacksection transistors are kept constant; the channel region length and thechannel region width of the gyrator core section transistors arereduced; and the transadmittance of the respective transistor is keptconstant such that the resonance frequency of the core section is largerthan the resonance frequency of the filter.
 5. The method according toclaim 1, wherein: the channel region dimensions of the gyrator coresection transistors are kept constant; and the channel region width ofcommon mode ballast inverters of the common mode feedback sectiontransistors is increased.
 6. The method according to claim 1, wherein:the channel region length of the gyrator core section transistors isreduced; the transadmittance of the respective transistor is changed;and the channel region width of the common mode feedback sectiontransistors is increased.
 7. The method according to claim 1, wherein:the channel region length and channel region width of the gyrator coresection transistors are reduced; the transadmittance of the respectivetransistor is kept constant; and the channel region width of the commonmode feedback section transistors is increased.
 8. The method accordingto claim 1, further comprising selecting all transistors in said commonmode feedback section and said gyrator core section to be identical. 9.The method according to claim 8, wherein: the transistors of each of theinverters include a transistor structure having a gate/source capacityC_(gs), a gate/drain capacity C_(gd), an output conductance g_(d) and atransadmittance y_(m) consisting of a resistive part g_(m) and acapacitive part c_(m); the values of g*C≧g_(m)*c_(m) are defined as:g=3gd C=C _(o)+3C _(gs)+6C _(gd); and C_(o) is the total effectivecapacitance between the gyrator core terminals due to at least one ofthe common mode feedback section and additional external capacitances.10. The method according to claim 1, further comprising selecting alltransistors in said common mode feedback section and said gyrator coresection to be different.
 11. The method according to claim 1, whereinthe channel length of the common mode inverters is increased.
 12. Themethod according to claim 1, wherein the channel length of the commonmode inverters is increased.
 13. A filter circuit comprising at leastone filter stage, the at least one filter stage comprising: a) a gyratorcore section having four inverters mutually connected in a loopconfiguration between a pair of input terminals and a pair of outputterminals; b) at least one common mode feedback section connectedbetween at least one of the the pair of input terminals and the pair ofoutput terminals and comprising two series connections respectivelyformed by an inverter and a shortsectioned inverter connectedantiparallely between at least one said input terminals and said outputterminals; c) each of said inverters comprising at least one MOS, CMOSor BiCMOS transistor, each of the at least one of a MOS, CMOS or BiCMOStransistors having a gate, drain, source, and a channel region betweensaid drain and source; d) wherein the channel region dimensions of thetransistors of at least one of the gyrator core section and the commonmode feedback section are selected such that the following relationshipis fulfilled: g*C≧g _(m) *c _(m); and where: g=effective conductiveloading of the gyrator core section terminals; C=effective capacitiveloading of the gyrator core section terminals; g_(m)=effective gyratingconstant of the gyrator core section; and c_(m)=effectivetranscapacitance of the gyrator core section.
 14. The filter circuitaccording to claim 13, wherein the channel region dimensions areselected to be different in said gyrator core section and in said commonmode feedback section.
 15. The filter circuit according to claim 13,wherein: the channel region dimensions of the common mode feedbacksection transistors are kept constant; the channel region length of thegyrator core section transistors is reduced; and the transadmittance ofthe respective transistor is changed.
 16. The filter circuit accordingto claim 13, wherein: the channel region dimensions of the common modefeedback section transistors are kept constant; the channel regionlength and the channel region width of the gyrator core sectiontransistors are reduced and; the transadmittance of the respectivetransistor is kept constant such that the resonance frequency of thecore section is larger than the resonance frequency of the filtercircuit.
 17. The filter circuit according to claim 13, wherein: thechannel region dimensions of the gyrator core section transistors arekept constant; and the channel region width of common mode ballastinverters of the common mode feedback section transistors is increased.18. The filter circuit according to claim 13, wherein: the channelregion length of the gyrator core section transistors is reduced; thetransadmittance of the respective transistor is changed; and the channelregion width of the common mode feedback section transistors isincreased.
 19. The filter circuit according to claim 13, wherein: thechannel region length and channel region width of the gyrator coresection transistors is reduced; the transadmittance of the respectivetransistor is kept constant; and the channel region width of the commonmode feedback section transistors is increased.
 20. The filter circuitaccording to claim 13, wherein all transistors in said common modefeedback section and said gyrator core section are identical.
 21. Thefilter circuit according to claim 20, wherein: the transistors of eachof the inverters comprise a transistor structure having a gate/sourcecapacity C_(gs), a gate/drain capacity C_(gd), an output conductanceg_(d), and a transadmittance y_(m) consisting of a resistive part g_(m)and a capacitive part c_(m); the values of g*C≧g_(m)*c_(m) are definedas: g=3g _(d); and C=C _(o)+3C _(gs)+6C _(gd); and C_(o) is the totaleffective capacitance between the gyrator core terminals due to thecommon mode feedback section and/or additional external capacitances.22. The filter circuit according to claim 13, wherein all transistors insaid common mode feedback section and said gyrator core section aredifferent.
 23. The filter circuit according to claim 13, wherein saidtransistors are operated in saturation.
 24. The filter circuit accordingto claim 13, wherein said filter circuit is a differential signal typefilter circuit.
 25. The method for making a filter circuit comprising atleast one filter stage, the method comprising: a) providing said atleast one filter stage with a gyrator core section having four invertersmutually connected in a feedback loop between a pair of input terminalsand a pair of output terminals; b) wherein the inverters are arranged asa differential transconductor configuration, such that a first andsecond inverter are respectively provided between the first input andfirst output terminal and the second input terminal and the secondoutput terminal; c) each of said inverters comprises at least one of aMOS, CMOS, and BiCMOS transistor, the at least one of a MOS, CMOS, andBiCMOS transistor having a gate, drain, source, and a channel regionbetween said drain and source; and d) selecting the general regiondimensions of the transistors of the gyrator core section such that thefollowing relationship is fulfilled: g*C≧g _(m) *c _(m), wherein where:g=effective conductive loading of the gyrator core section terminals;C=effective capacitive loading of the gyrator core section terminals;g_(m)=effective gyrating constant of the gyrator core section; andc_(m)=effective transcapacitance of the gyrator core section.
 26. Themethod according to claim 25, wherein: the channel region length of thegyrator core section transistors is reduced; and the transmittance ofthe respective transistor is changed.
 27. The method according to claim25, wherein: the channel region length and the channel region width ofthe gyrator core section transistors is reduced; and the transadmittanceof the respective transistor is kept constant.
 28. The filter circuitcomprising: a) at least one filter stage with a gyrator core sectionhaving four inverters mutually connected in a feedback loop between apair of input terminals and a pair of output terminals; b) wherein theinverters are arranged as a differential transconductor configuration,such that a first and second inverter are respectively provided betweenthe first input and first output terminal and the second input terminaland the second output terminal; c) wherein each of said inverterscomprises at least one of a MOS, CMOS, and BiCMOS transistor, the atleast one of a MOS, CMOS, and BiCMOS transistor having a gate, drain,source, and a channel region between said drain and source; d) whereinthe general region dimensions of the transistors of the gyrator coresection are selected such that the following relationship is fulfilled:g*C≧g _(m) *c _(m); where: g=effective conductive loading of the gyratorcore section terminals; C=effective capacitive loading of the gyratorcore section terminals; g_(m)=effective gyrating constant of the gyratorcore section; and c_(m)=effective transcapacitance of the gyrator coresection.
 29. The filter circuit according to claim 28, wherein: thechannel region length of the gyrator core section transistors isreduced; and the transmittance of the respective transistor is changed.30. The filter circuit according 28, wherein: the channel region lengthand the channel region width of the gyrator core section transistors isreduced; and the transadmittance of the respective transistor is keptconstant.